1. Field of the Invention
The present invention relates to an information processing apparatus which stores importance information in a plurality of memories, and a control method therefor.
2. Description of the Related Art
An information processing apparatus generally adopts a mechanism of writing importance information in a plurality of semiconductor memories to back up the importance information which must be held even upon normal power-off, generation of noise during write in a memory, or unexpected power-off. A multi-functional peripheral (to be referred to as an MFP hereinafter) for an image processing apparatus serving as an information processing apparatus will be exemplified. Importance information in the MFP includes, for example, the counter value of the print count used for the charging function, the main set values of the device, the telephone book of the FAX function, and the address list of the e-mail function, which are set values and save values hard to input again once they are lost.
FIG. 14 is a block diagram showing the arrangement of an information processing apparatus 1400. In the information processing apparatus 1400, as shown in FIG. 14, importance information is written at different timings from an SOC (System On Chip) 1250 in SRAMs 1210 and 1220 and an FRAM 1240 of an importance information backup unit 105 via parallel IFs. The same value is stored in three memories to reduce the possibility of loss. The SOC is a chip which integrates a CPU and ASIC and mounts them in a single package.
FIG. 15 is a timing chart showing the timings of write in memories in the information processing apparatus 1400. FIG. 16 is a timing chart showing the timings of read from the memories in the information processing apparatus 1400. As shown in FIGS. 15 and 16, the information processing apparatus 1400 executes write or read in or from memories at different timings. The SRAM is a volatile memory and separately requires a battery circuit 1230. The FRAM is more expensive than an EEPROM which is a nonvolatile memory similar to the FRAM. The arrangement of the information processing apparatus 1400 raises the cost, compared to forming a memory from an EEPROM.
From this, there is proposed an information processing apparatus 1700 shown in FIG. 17 which reduces the cost of the information processing apparatus 1400. FIG. 17 is a block diagram showing the arrangement of the information processing apparatus 1700. In the information processing apparatus 1700, importance information is written at different timings from an SOC 1260 in serial EEPROMs 1270, 1280, and 1290 of an importance information backup unit 105 via serial IFs. Compared to the information processing apparatus 1400, the information processing apparatus 1700 reduces the cost by using an EEPROM as the memory and a serial interface as the interface.
FIG. 18 is a timing chart showing the timings of write in memories in the information processing apparatus 1700. FIG. 19 is a timing chart showing the timings of read from the memories in the information processing apparatus 1700. As shown in FIGS. 18 and 19, the speeds of write and read in and from the memory of the information processing apparatus 1700 are lower than those in the information processing apparatus 1400. The main cause is that the memory interface of the information processing apparatus 1700 is a serial interface. A long memory access time decreases software performance. At the same time, a long memory access time increases the possibility of garbled data under the influence of noise or unexpected power-off.
Japanese Patent Laid-Open No. 2004-110407 (patent reference 1) proposes a serial EEPROM which easily notifies the end of write without frequent polling by the CPU in order to lighten the software load of a host CPU.
However, the conventional technique suffers the following problems. As described above, the information processing apparatus 1400 achieves a satisfactory memory access speed, but the cost is high because the SRAM separately requires a battery circuit and the FRAM is expensive. The information processing apparatus 1700 can reduce the cost by using a serial IF EEPROM, but decreases the memory access speed. In the information processing apparatus 1700, the memory access time is prolonged to decrease software performance. In addition, the long memory access time increases the possibility of garbled data under the influence of noise or unexpected power-off. According to patent reference 1, the process load of the host CPU can be reduced, but no measure against data garbled by a long memory access time is proposed.